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general description the MAX1270/max1271 are multirange, 12-bit data- acquisition systems (das) that require only a single +5v supply for operation, yet accept signals at their analog inputs that can span above the power-supply rail and below ground. these systems provide eight analog input channels that are independently software programmable for a variety of ranges: ?0v, ?v, 0 to +10v, 0 to +5v for the MAX1270; ? ref , ? ref /2, 0 to v ref , 0 to v ref /2 for the max1271. this range switch- ing increases the effective dynamic range to 14 bits and provides the flexibility to interface 4?0ma, ?2v, and ?5v powered sensors directly to a single +5v system. in addition, these converters are fault protected to ?6.5v; a fault condition on any channel will not affect the conversion result of the selected channel. other fea- tures include a 5mhz bandwidth track/hold, software- selectable internal/external clock, 110ksps throughput rate, and internal 4.096v or external reference operation. the MAX1270/max1271 serial interface directly connects to spi/qspi and microwire devices without external logic. a hardware shutdown input ( shdn ) and two software- programmable power-down modes, standby (stbypd) or full power-down (fullpd), are provided for low-cur- rent shutdown between conversions. in standby mode, the reference buffer remains active, eliminating startup delays. the MAX1270/max1271 are available in 24-pin narrow pdip or space-saving 28-pin ssop packages. applications features ? 12-bit resolution, 0.5 lsb linearity ? +5v single-supply operation ? spi/qspi and microwire-compatible 3-wire interface ? four software-selectable input ranges MAX1270: 0 to +10v, 0 to +5v, 10v, 5v max1271: 0 to v ref , 0 to v ref /2, v ref , v ref /2 ? eight analog input channels ? 110ksps sampling rate ? 16.5v overvoltage-tolerant input multiplexer ? internal 4.096v or external reference ? two power-down modes ? internal or external clock ? 24-pin narrow pdip or 28-pin ssop packages MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs ________________________________________________________________ maxim integrated products 1 v dd ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 dgnd 4.7 f 0.1 f 0.01 f shdn MAX1270 max1271 +5v analog inputs cs sclk din dout sstrb i/o sck mosi miso ref refadj agnd mc68hcxx t ypical operating circuit part temp range pin-package inl (lsb) MAX1270 acng 0? to +70? 24 narrow pdip ?.5 MAX1270bcng 0? to +70? 24 narrow pdip ? MAX1270acai 0? to +70? 28 ssop ?.5 MAX1270bcai 0? to +70? 28 ssop ? ordering information 19-4782; rev 2; 9/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configurations appear at end of data sheet. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. ordering information continued at end of data sheet. evaluation kit available industrial control systems data-acquisition systems battery-powered instruments automatic testing robotics medical instruments
MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +5.0v 5%; unipolar/bipolar range; external reference mode, v ref = +4.096v; 4.7f at ref; external clock; f clk = 2.0mhz, 50% duty cycle (max127_b); f clk = 1.8mhz, 50% duty cycle (max127_a); 18 clock/conversion cycle, t a = t min to t max , unless otherwise noted. typical values are t a = +25?c.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd............................................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v ch0ech7 to agnd ......................................................... 16.5v ref, refadj to agnd ..............................-0.3v to (v dd + 0.3v) sstrb, dout to dgnd.............................-0.3v to (v dd + 0.3v) shdn , cs , din, sclk to dgnd..............................-0.3v to +6v max current into any pin ....................................................50ma continuous power dissipation (t a = +70?c) 24-pin narrow dip (derate 13.33mw/?c above +70?c)..1067mw 28-pin ssop (derate 9.52mw/?c above +70?c) ..........762mw operating temperature ranges max127_c_ _......................................................0?c to +70?c max127_e_ _......................................................-40?c to +85?c storage temperature range .............................-65?c to +150?c lead temperature (soldering, 10s) .................................+300?c parameter symbol conditions min typ max units accuracy (note 1) resolution 12 bits max127_a 0.5 integral nonlinearity inl max127_b 1.0 lsb differential nonlinearity dnl no missing codes over temperature 1 lsb max127_a 3 unipolar max127_b 5 max127_a 5 offset error bipolar max127_b 10 lsb unipolar 0.1 channel-to-channel offset error matching bipolar 0.3 lsb max127_a 7 unipolar max127_b 10 max127_a 7 gain error (note 2) bipolar max127_b 10 lsb unipolar, external reference 3 gain error temperature coefficient (note 2) bipolar, external reference 5 ppm/?c dynamic specifications (10khz sine-wave input, 10v p-p (MAX1270), or 4.096v p-p (max1271), f sample = 110ksps (max127_b), f sample = 100ksps (max127_a)) signal-to-noise + distortion ratio sinad 70 db total harmonic distortion thd up to the 5th harmonic -87 -78 db spurious-free dynamic range sfdr 80 db 50khz (note 3) -86 channel-to-channel crosstalk dc, v in = 16.5v -96 db aperture delay external clock mode 15 ns external clock mode <50 ps aperture jitter internal clock mode 10 ns
MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +5.0v 5%; unipolar/bipolar range; external reference mode, v ref = +4.096v; 4.7f at ref; external clock; f clk = 2.0mhz, 50% duty cycle (max127_b); f clk = 1.8mhz, 50% duty cycle (max127_a); 18 clock/conversion cycle, t a = t min to t max , unless otherwise noted. typical values are t a = +25?c.) parameter symbol conditions min typ max units analog input max127_a, f clk = 1.8mhz 3.3 track/hold acquisition time t acq max127_b, f clk = 2.0mhz 3.0 s 10v or v ref range 5 5v or v ref /2 range 2.5 0 to 10v or 0 to v ref range 2.5 small-signal bandwidth -3db rolloff 0 to 5v or 0 to v ref /2 range 1.25 mhz rng = 1 0 10 MAX1270 rng = 0 0 5 rng = 1 0 v ref unipolar (bip = 0), table 3 max1271 rng = 0 0 v ref /2 rng = 1 -10 +10 MAX1270 rng = 0 -5 +5 rng = 1 -v ref +v ref input voltage range (table 3) v in bipolar (bip = 1), table 3 max1271 rng = 0 -v ref /2 +v ref / 2 v 0 to 10v range -10 +720 MAX1270 0 to 5v range -10 +360 unipolar max1271 -10 0.1 +10 10v range -1200 +720 MAX1270 5v range -600 +360 v ref range -1200 +10 input current i in bipolar max1271 v ref /2 range -600 +10 a unipolar 21 dynamic resistance ? ? ?
MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = +5.0v 5%; unipolar/bipolar range; external reference mode, v ref = +4.096v; 4.7f at ref; external clock; f clk = 2.0mhz, 50% duty cycle (max127_b); f clk = 1.8mhz, 50% duty cycle (max127_a); 18 clock/conversion cycle, t a = t min to t max , unless otherwise noted. typical values are t a = +25?c.) parameter symbol conditions min typ max units internal reference ref output voltage v ref t a = +25?c 4.076 4.096 4.116 v MAX1270_c/max1271_c 15 ref output tempco tc v ref MAX1270_e/max1271_e 30 ppm/ c output short-circuit current 30 ma load regulation 0 to 0.5ma output current (note 5) 10 mv capacitive bypass at ref 4.7 f capacitive bypass at refadj 0.01 f refadj output voltage 2.465 2.500 2.535 v refadj adjustment range figure 1 1.5 % buffer voltage gain 1.638 v/v reference input (reference buffer disabled, reference input applied to ref) input voltage range 2.40 4.18 v normal or stbypd 400 input current v ref = 4.18v fullpd 1 a normal or stbypd 10 k ? ? 0.1 0.5 power-supply rejection ratio (note 7) psrr internal reference 0.5 lsb timing max127_a 0.1 1.8 external clock frequency range f sclk max127_b 0.1 2.0 mhz max127_a 3.3 external clock mode (note 8) max127_b 3.0 acquisition phase internal clock mode, figure 9 3 5 s
MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs _______________________________________________________________________________________ 5 electrical characteristics (continued) (v dd = +5.0v 5%; unipolar/bipolar range; external reference mode, v ref = +4.096v; 4.7f at ref; external clock; f clk = 2.0mhz, 50% duty cycle (max127_b); f clk = 1.8mhz, 50% duty cycle (max127_a); 18 clock/conversion cycle, t a = t min to t max , unless otherwise noted. typical values are t a = +25?c.) parameter symbol conditions min typ max units max127_a 6.6 external clock mode (note 8) max127_b 6.0 conversion time t conv internal clock mode, figure 9 6 7.7 11 s max127_a 100 external clock mode max127_b 110 throughput rate internal clock mode 43 ksps bandgap reference startup time power-up (note 9) 200 s c ref = 4.7f 8 reference buffer settling time to 0.1mv, ref bypass capacitor fully discharged c ref = 33f 60 ms digital inputs (din, sclk, cs , and shdn ) input high threshold voltage v ih 2.4 v input low threshold voltage v il 0.8 v input hysteresis v hys 0.2 v input leakage current i in v in = 0 to v dd -10 +10 a input capacitance c in (note 4) 15 pf digital outputs (dout, sstrb) i sink = 5ma 0.4 output voltage low v ol i sink = 16ma 0.4 v output voltage high v oh i source = 0.5ma v dd - 0.5 v tri-state leakage current i l cs dd sc c cs dd n
MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs 6 _______________________________________________________________________________________ note 1: accuracy specifications tested at v dd = +5.0v. performance at power-supply tolerance limit is guaranteed by power-supply rejection test. note 2: external reference: v ref = 4.096v, offset error nulled. ideal last-code transition = fs - 3/2 lsb. note 3: ground on channel; sine wave applied to all off channels. v in = 5v (MAX1270), v in = 4v (max1271). note 4: guaranteed by design, not production tested. note 5: use static external loads during conversion for specified accuracy. note 6: tested using internal reference. note 7: psrr measured at full scale. tested for the 10v (MAX1270) and 4.096v (max1271) input ranges. note 8: acquisition phase and conversion time are dependent on the clock period; clock has 50% duty cycle (figure 6). note 9: not production tested. provided for design guidance only. timing characteristics (v dd = +4.75v to +5.25v; unipolar/bipolar range; external reference mode, v ref = +4.096v; 4.7f at ref; external clock; f clk = 2.0mhz (max127_b); f clk = 1.8mhz (max127_a); t a = t min to t max , unless otherwise noted. typical values are t a = +25?c.) (figures 2, 5, 7, 10) parameter symbol conditions min typ max units din to sclk setup t ds 100 ns din to sclk hold t dh 0ns sclk fall to output data valid t do 20 170 ns cs fall to output enable t dv c load = 100pf 120 ns cs rise to output disable t tr c load = 100pf 100 ns cs to sclk rise setup t css 100 ns cs to sclk rise hold t csh 0ns sclk pulse-width high t ch 200 ns sclk pulse-width low t cl 200 ns sclk fall to sstrb t sstrb c load = 100pf 200 ns cs to sstrb output enable t sdv c load = 100pf, external clock mode only 200 ns cs to sstrb output disable t str c load = 100pf, external clock mode only 200 ns sstrb rise to sclk rise t sck internal clock mode only (note 4) 0 ns
MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs _______________________________________________________________________________________ 7 t ypical operating characteristics (typical operating circuit, v dd = +5v; external reference mode, v ref = +4.096v; 4.7? at ref; external clock, f clk = 2mhz; 110ksps; t a = +25?, unless otherwise noted.) 0 5 15 10 20 25 02 1 34567 supply current vs. supply voltage MAX1270/1 toc01 supply voltage (v) supply current (ma) 5.5 5.7 6.1 5.9 6.3 6.5 -40 10 -15 35 60 85 supply current vs. temperature MAX1270/1 toc02 temperature ( c) supply current (ma) 50 150 450 350 250 650 550 750 -40 10 -15 35 60 85 standby supply current vs. temperature MAX1270/1 toc03 temperature ( c) standby supply current ( a) internal reference external reference 50 70 110 90 130 150 -40 10 -15 35 60 85 full power-down supply current vs. temperature MAX1270/1 toc04 temperature ( c) full power-down supply current ( a) internal reference external reference 0.1 0.2 0.6 0.5 0.4 0.3 0.7 0.8 -40 10 -15 35 60 85 channel-to-channel gain-error matching vs. temperature MAX1270/1 toc07 temperature ( c) channel-to-channel gain-error matching (lsb) bipolar mode unipolar mode 0.996 0.997 0.999 0.998 1.000 1.001 -40 10 -15 35 60 85 normalized reference voltage vs. temperature MAX1270/1 toc05 temperature ( c) normalized reference voltage 0 0.05 0.25 0.20 0.15 0.10 0.30 0.35 -40 10 -15 35 60 85 channel-to-channel offset-error matching vs. temperature MAX1270/1 toc06 temperature ( c) channel-to-channel offset-error matching (lsb) bipolar mode unipolar mode -0.15 -0.10 0.05 0 -0.05 0.10 0.15 0 1638 819 2457 3276 4095 integral nonlinearity vs. digital code MAX1270/1 toc08 digital code integral nonlinearity (lsb) -120 -100 -40 -60 -80 -20 0 0 20k 10k 30k 40k 50k ftt plot MAX1270/1 toc09 frequency (hz) amplitude (db) f in = 10khz f sample = 110ksps
MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs 8 _______________________________________________________________________________________ pin description pin pdip ssop name function 11 v dd +5v supply. bypass with a 0.1? capacitor to agnd. 2, 4 2, 3 dgnd digital ground 3, 9, 22, 24 4, 7, 8, 11, 22, 24, 25, 28 n.c. no connection. no internal connection. 55 sclk serial clock input. clocks data in and out of serial interface. in external clock mode, sclk also sets the conversion speed. 66 cs active-low chip-select input. data is not clocked into din unless cs is low. when cs is high, dout is high impedance. 79 din serial data input. data is clocked in on the rising edge of sclk. 810 sstrb serial strobe output. in internal clock mode, sstrb goes low after the falling edge of the eighth sclk and returns high when the conversion is done. in external clock mode, sstrb pulses high for one clock period before the msb decision. high impedance when cs is high in external clock mode. 10 12 dout serial data output. data is clocked out on the falling edge of sclk. high impedance when cs is high. 11 13 shdn shutdown input. when low, device is in fullpd mode. connect high for normal operation. 12 14 agnd analog ground 13?0 15?1, 23 ch0?h7 analog input channels 21 26 refadj bandgap voltage-reference output/external adjust pin. bypass with a 0.01? capacitor to agnd. connect to v dd when using an external reference at ref. 23 27 ref refer ence- buffer o utp u t/ad c refer ence inp ut. in i nter nal r efer ence m od e, the r efer ence b u ffer p r ovi d es a 4.096v nom i nal outp ut, exter nal l y ad j ustab l e to re fad j. in exter nal r efer e nce m od e, d i sab l e the i nter nal r efer e nce b y p ul l i ng re fad j to v d d and ap p l yi ng the exter nal r efer ence to re f. 0 1 2 3 4 5 6 7 8 0.1 1 10 100 1000 average supply current vs. conversion rate (using standby) MAX1270-toc10 conversion rate (ksps) average supply current (ma) v dd = 5v, internal reference, f clk = 2mhz external clock mode. low-range unipolar mode. v ch_ = 0 0 1 2 3 4 5 6 7 8 0.1 1 10 100 1000 average supply current vs. conversion rate (using fullpd) MAX1270-toc11 conversion rate (ksps) average supply current (ma) v dd = 5v, internal reference, f clk = 2mhz external clock mode. low-range unipolar mode. v ch_ = 0 t ypical operating characteristics (continued) (typical operating circuit, v dd = +5v; external reference mode, v ref = +4.096v; 4.7? at ref; external clock, f clk = 2mhz; 110ksps; t a = +25?, unless otherwise noted.)
MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs _______________________________________________________________________________________ 9 detailed description converter operation the MAX1270/max1271 multirange, fault-tolerant adcs use successive approximation and internal track/hold (t/h) circuitry to convert an analog signal to a 12-bit digital output. figure 3 shows the block diagram of the MAX1270/max1271. analog-input track/hold the t/h enters tracking/acquisition mode on the falling edge of the sixth clock in the 8-bit input control word, and enters hold/conversion mode when the timed acquisition interval (six clock cycles, 3s minimum) ends. in internal clock mode, the acquisition is timed by two external clock cycles and four internal clock cycles. when operating in bipolar (MAX1270 and max1271) or unipolar mode (MAX1270) the signal applied at the input channel is rescaled through the resistor-divider network formed by r1, r2, and r3 (figure 4); a low impedance (<4 ? ) input source is recommended to minimize gain error. when the max1271 is configured for unipolar mode, the channel input resistance (r in ) becomes a fixed 5.12k ? (typ). source impedances below 15k ? (0 to v ref ) and 5k ? (0 to v ref /2) do not significantly affect the ac performance of the adc. the acquisition time (t acq ) is a function of the source output resistance, the channel input resistance, and the t/h capacitance. higher source impedances can be used if an input capacitor is connected between the analog inputs and agnd. note that the input capacitor forms an rc filter with the input source impedance, lim- iting the adc? signal bandwidth. 100k ? 510k ? 24k ? refadj +5v MAX1270 max1271 0.01 f ch2 ch1 ch0 shdn ch3 ch4 ch5 ch6 ch7 refadj ref v dd agnd dgnd MAX1270 max1271 12-bit sar adc in ref clock out t/h 2.5v reference analog input mux and signal conditioning av = 1.638 int clock din sstrb dout cs sclk serial interface logic 10k ? +4.096v 0.5ma dout or sstrb +5v a) high impedance to v oh , v ol to v oh and v oh to high impedance high impedance to v oh , v ol to v oh and v oh to high impedance b) c load c load 5ma dout or sstrb figure 1. reference-adjust circuit figure 3. block diagram figure 2. output load circuit for timing characteristics
MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs 10 ______________________________________________________________________________________ input bandwidth the adc? input small-signal bandwidth depends on the selected input range and varies from 1.5mhz to 5mhz (see electrical characteristics ). the MAX1270b/ max1271b maximum sampling rate is 110ksps (100ksps for the MAX1270a/max1271a). by using undersampling techniques, it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate. to avoid high-frequency signals being aliased into the frequency band of interest, anti-aliasing filtering is rec- ommended. input range and protection the MAX1270/max1271 have software-selectable input ranges. each analog input channel can be indepen- dently programmed to one of four ranges by setting the appropriate control bits (rng, bip) in the control byte (table 1). the MAX1270 has selectable input ranges extending to ?0v (? ref x 2.441), while the max1271 has selectable input ranges extending to ? ref . figure 4 shows the equivalent input circuit. a resistor network on each analog input provides ?6.5v fault protection for all channels. whether or not the channel is on, this circuit limits the current going into or out of the pin to less than 2ma. this provides an added layer of protection when momentary overvolt- ages occur at the selected input channel, when a neg- ative signal is applied to the input, and when the device is configured for unipolar mode. the overvoltage pro- tection is active even if the device is in power-down mode or if v dd = 0. digital interface the MAX1270/max1271 feature a serial interface that is fully compatible with spi/qspi and microwire devices. for spi/qspi, set cpol = 0, cpha = 0 in the spi control registers of the microcontroller. figure 5 shows detailed serial-interface timing information. see table 1 for details on programming the input control byte. t csh t css t cl t ds t dh t dv t ch t do t tr t csh cs sclk din dout figure 5. detailed serial-interface timing r3 5.12k ? r2 r1 ch_ s1 s2 s3 s4 bipolar unipolar voltage reference t/h out hold track track hold off on c hold s1 = bipolar/unipolar switch s2 = input mux switch s3, s4 = t/h switch r1 = 12.5k ? (MAX1270) or 5.12k ? (max1271) r2 = 8.67k ? (MAX1270) or (max1271) figure 4. equivalent input circuit
MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs ______________________________________________________________________________________ 11 table 1. control-byte format bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) start sel2 sel1 sel0 rng bip pd1 pd0 bit name description 7 (msb) start first logic 1 after cs goes low defines the beginning of the control byte. 6, 5, 4 sel2, sel1, sel0 these 3 bits select the desired ?n?channel (table 2). 3 rng selects the full-scale input voltage range (table 3). 2 bip selects the unipolar or bipolar conversion mode (table 3). 1, 0 (lsb) pd1, pd0 select clock and power-down modes (table 4). table 2. channel selection sel2 sel1 sel0 channel 000 ch0 001 ch1 010 ch2 011 ch3 100 ch4 101 ch5 110 ch6 111 ch7 table 4. power-down and clock selection pd1 pd0 m ode 00 normal operation (always on), internal clock mode. 01 normal operation (always on), external clock mode. 10 standby power-down mode (stbypd), clock mode unaffected. 11 full power-down mode (fullpd), clock mode unaffected. table 3. range and polarity selection for MAX1270/max1271 range and polarity selection for the MAX1270 input range rng bip negative full scale zero scale (v) full scale 0 to +5v 0 0 0 v ref x 1.2207 0 to +10v 1 0 0 v ref x 2.4414 5v 0 1 -v ref x 1.2207 0 v ref x 1.2207 10v 1 1 -v ref x 2.4414 0 v ref x 2.4414 range and polarity selection for the max1271 input range rng bip negative full scale zero scale (v) full scale 0 to v ref /2 0 0 0 v ref /2 0 to v ref 10 0 v ref v ref /2 0 1 -v ref /2 0 v ref /2 v ref 11 -v ref 0v ref
MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs 12 ______________________________________________________________________________________ input data format input data (control byte) is clocked in at din at the ris- ing edge of sclk. cs enables communication with the MAX1270/max1271. after cs falls, the first arriving logic 1 bit represents the start bit (msb) of the input control byte. the start bit is defined as: the first high bit clocked into din with cs low anytime the converter is idle; e.g., after v dd is applied. or the first high bit clocked into din after bit 6 (d6) of a conversion in progress is clocked onto dout. output data format output data is clocked out on the falling edge of sclk at dout, msb first (d11). in unipolar mode, the output is straight binary. for bipolar mode, the output is two? complement binary. for output binary codes, refer to the transfer function section. how to start a conversion the MAX1270/max1271 use either an external serial clock or the internal clock to complete an acquisition and perform a conversion. in both clock modes, the external clock shifts data in and out. see table 4 for details on programming clock modes. the falling edge of cs does not start a conversion on the MAX1270/max1271; a control byte is required for each conversion. acquisition starts after the sixth bit is programmed in the input control byte. conversion starts when the acquisition time, six clock cycles, expires. keep cs low during successive conversions. if a start- bit is received after cs transitions from high to low, but before the output bit 6 (d6) becomes available, the cur- rent conversion will terminate and a new conversion will begin. external clock mode (pd1 = 0, pd0 = 1) in external clock mode, the clock shifts data in and out of the MAX1270/max1271 and controls the acquisition and conversion timings. when acquisition is done, sstrb pulses high for one clock cycle and conversion begins. successive-approximation bit decisions appear at dout on each of the next 12 sclk falling edges (figure 6). additional sclk falling edges will result in zeros appearing at dout. figure 7 shows the sstrb timing in external clock mode. sstrb and dout go into a high-impedance state when cs goes high; after the next cs falling edge, sstrb and dout will output a logic low. the conversion must be completed in some minimum time, or droop on the sample-and-hold capacitors may degrade conversion results. use internal clock mode if the clock period exceeds 10?, or if serial-clock inter- ruptions could cause the conversion interval to exceed 120?. the fastest the MAX1270/max1271 can run is 18 clocks per conversion in external clock mode, and with a clock rate of 2mhz, the maximum sampling rate is 111 ksps (figure 8). in order to achieve maximum throughput, keep cs low, use external clock mode with a continuous sclk, and start the following control byte after bit 6 (d6) of the conversion in progress is clocked onto dout. if cs is low and sclk is continuous, guarantee a start bit by first clocking in 18 zeros. sstrb cs sclk din dout 1812 13 14 24 25 start sel2 sel1 sel0 bip rng pd1 pd0 lsb d11 msb msb d10 d9 d1 d0 lsb acquisition 6 sclk filled with zeros conversion 12 sclk a/d state high-z high-z high-z high-z figure 6. external clock mode?5 clocks/conversion timing
MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs ______________________________________________________________________________________ 13 internal clock mode (pd1 = 0, pd0 = 0) in internal clock mode, the MAX1270/max1271 gener- ate their conversion clock internally. this frees the microprocessor from the burden of running the acquisi- tion and the sar conversion clock, and allows the con- version results to be read back at the processor? convenience, at any clock rate from 0 to typically 10mhz. sstrb goes low after the falling edge of the last bit (pd0) of the control byte has been shifted in, and returns high when the conversion is complete. acquisition is completed and conversion begins on the falling edge of the 4th internal clock pulse after the con- trol byte; conversion ends on the falling edge of the 16th internal clock pulse (12 internal clock cycle pulses are used for conversion). sstrb will remain low for a maximum of 15?, during which time sclk should remain low for best noise performance. an internal reg- ister stores data while the conversion is in progress. the msb of the result byte (d11) is present at dout starting at the falling edge of the last internal clock of conversion. successive falling edges of sclk will shift the remaining data out of this register (figure 9). additional sclk edges will result in zeros on dout. when internal clock mode is selected, sstrb does not go into a high-impedance state when cs goes high. pulling cs high prevents data from being clocked in and tri-states dout, but does not adversely affect a t sdv t sstrb sclk 12 t str sstrb sclk cs t sstrb high-z high-z figure 7. external clock mode?strb detailed timing cs sclk din dout a/d state 13 19 24 26 31 32 14 16 37 start sel2 sel1 sel0 bip rng pd1 pd0 d11 d10 d9 d7 d8 d6 d5 d4 d2 d3 d1 d0 lsb 8 1 msb lsb msb start sel2 sel1 sel0 bip rng pd1 pd0 start sel2 control byte 0 result control byte 1 control byte 2 18 sclk 18 sclk sstrb d10 d11 d9 d8 d6 d7 d5 result 1 acquisition 6 sclk conversion 12 sclk acquisition 6 sclk conversion 12 sclk high-z high-z figure 8. external clock mode?8 clocks/conversion timing
MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs 14 ______________________________________________________________________________________ conversion in progress. figure 10 shows the sstrb timing in internal clock mode. internal clock mode conversions can be completed with 13 external clocks per conversion but require a waiting period of 15? for the conversion to be com- pleted (figure 11). most microcontrollers require that conversions occur in multiples of 8 sclk clock cycles. sixteen clock cycles per conversion (as shown in figure 12) is typically the most convenient way for a microcontroller to drive the MAX1270/max1271. applications information power-on reset the MAX1270/max1271 power up in normal operation (all internal circuitry active) and internal clock mode, waiting for a start bit. the contents of the output data register are cleared at power-up. internal or external reference the MAX1270/max1271 operate with either an internal or external reference. an external reference is connect- ed to either ref or refadj (figure 13). the refadj internal buffer gain is trimmed to 1.638v to provide 4.096v at ref from a 2.5v reference. sstrb cs sclk din dout 1 8 20 start sel2 sel1 sel0 rng bip pd1 pd0 d11 d10 d1 d0 acquisition filled with zeros conversion a/d state 910 19 16 int clk 12 int clk msb lsb msb lsb 2 ext sclk +4 int clk high-z high-z high-z figure 9. internal clock mode?0 sclk/conversion timing sclk #8 t sstrb t csh t sck t css note: for best noise performance, keep sclk low during conversion. sstrb sclk cs figure 10. internal clock mode?strb detailed timing
MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs ______________________________________________________________________________________ 15 internal reference the internally trimmed 2.50v reference is amplified through the refadj buffer to provide 4.096v at ref. bypass ref with a 4.7? capacitor to agnd and refadj with a 0.01? capacitor to agnd (figure 13a). the internal reference voltage is adjustable to ?.5% (?5 lsbs) with the reference-adjust circuit of figure 1. external reference to use the ref input directly, disable the internal buffer by tying refadj to v dd (figure 13b). using the refadj input eliminates the need to buffer the refer- ence externally. when a reference is applied at refadj, bypass refadj with a 0.01? capacitor to agnd. note that when an external reference is applied at refadj, the voltage at ref is given by: v ref = 1.6384 x v refadj (2.4 < v ref < 4.18) (figure 13c). at ref and refadj, the input impedance is a minimum of 10k ? for dc currents. during conver- sions, an external reference at ref must be able to deliv- er 400? dc load currents and must have an output impedance of 10 ? or less. if the reference has higher output impedance or is noisy, bypass ref with a 4.7? capacitor to agnd as close to the chip as possible. with an external reference voltage of less than 4.096v at ref or less than 2.5v at refadj, the increase in the ratio of rms noise to the lsb value (full-scale / 4096) results in performance degradation (loss of effective bits). cs sclk din dout a/d state 1 8 9 24 22 14 16 start sel2 sel1 sel0 bip rng pd1 pd0 d11 d10 d9 d7 d8 d6 d5 d4 d2 d3 d1 d0 start sel2 sel1 sel0 bip rng pd1 pd0 start sel0 sel1 sel2 control byte result control byte 1 control byte 2 13 sclk 13 sclk sstrb d10 d11 d9 d8 d6 d7 d5 d4 d3 result 1 acquisition conversion acquisition conversion high-z figure 11. internal clock mode?3 clocks/conversion timing cs sclk din dout a/d state idle 9 24 25 32 16 17 start start sel2 sel1 sel0 bip rng pd1 pd0 d11 d10 d9 d7 d8 d6 d5 d4 d2 d3 d1 d0 start sel2 sel1 sel0 bip rng pd1 pd0 control byte result control byte 1 cb 2 16 sclk 16 sclk sstrb d10 d11 d9 d8 d6 d7 d5 d4 d3 result 1 acquisition conversion acquisition conversion high-z high-z high-z 1 8 figure 12. internal clock mode?6 clocks/conversion timing
MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs 16 ______________________________________________________________________________________ power-down mode to save power, configure the converter into low-current shutdown mode between conversions. two program- mable power-down modes are available in addition to a hardware shutdown. select stbypd or fullpd by pro- gramming pd0 and pd1 in the input control byte (table 4). when software power-down is asserted, it becomes effective only after the end of conversion. for example, if the control byte contains pd1 = 0, then the chip remains powered up. if pd1 = 1, then the chip powers down at the end of conversion. in all power- down modes, the interface remains active and conver- sion results can be read. input overvoltage protection is active in all power-down modes. the first logical 1 on din after cs falls is interpreted as a start condition, and powers up the MAX1270/ max1271 from a software selected stbypd or fullpd condition. for hardware-controlled power-down (fullpd), pull shdn low. when hardware shutdown is asserted, it becomes effective immediately, and any conversion in progress is aborted. choosing power-down modes the bandgap reference and reference buffer remain active in stbypd mode, maintaining the voltage on the 4.7? capacitor at ref. this is a dc state that does not degrade after power-down of any duration. in fullpd mode, only the bandgap reference is active. connect a 33? capacitor between ref and agnd to maintain the reference voltage between conversions and to reduce transients when the buffer is enabled and disabled. throughput rates down to 1ksps can be achieved without allotting extra acquisition time for ref- erence recovery prior to conversion. this allows con- version to begin immediately after power-up. if the discharge of the ref capacitor during fullpd exceeds the desired limits for accuracy (less than a fraction of an lsb), run a stbypd power-down cycle prior to starting conversions. take into account that the reference buffer recharges the bypass capacitor at an 80mv/ms slew rate, and add 50? for settling time. auto-shutdown selecting stbypd on every conversion automatically shuts down the MAX1270/max1271 after each conversion without requiring any start-up time on the next conversion. ref 10k ? 2.5v 2.5v refadj a v = 1.638 MAX1270 max1271 4.7 f c ref 0.01 f figure 13c. external reference?eference at refadj ref v dd 10k ? 2.5v 4.096v refadj a v = 1.638 MAX1270 max1271 4.7 f c ref figure 13b. external reference?eference at ref ref 10k ? 2.5v refadj 0.01 f a v = 1.638 MAX1270 max1271 4.7 f c ref figure 13a. internal reference
MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs ______________________________________________________________________________________ 17 transfer function output data coding for the MAX1270/max1271 is bina- ry in unipolar mode with 1 lsb = (fs / 4096) and two?s complement binary in bipolar mode with 1 lsb = [(2 x | fs | ) / 4096]. code transitions occur halfway between successive-integer lsb values. figures 14a and 14b show the input/output (i/o) transfer functions for unipo- lar and bipolar operations, respectively. for full-scale values, refer to table 3. layout, grounding, and bypassing careful pc board layout is essential for best system performance. use a ground plane for best perfor- mance. to reduce crosstalk and noise injection, keep analog and digital signals separate. connect analog grounds and dgnd in a star configuration to agnd. for noise-free operation, ensure the ground return from agnd to the supply ground is low impedance and as short as possible. connect the logic grounds directly to the supply ground. bypass v dd with 0.1f and 4.7f capacitors to agnd to minimize highand low-frequency fluctuations. if the supply is excessively noisy, connect a 5 1 resistor between the supply and v dd , as shown in figure 15. v dd gnd dgnd dgnd agnd +5v +5v supply r* = 5 digital circuitry 4.7 f 0.1 f MAX1270 max1271 ** *optional **connect agnd and dgnd with a ground plane or a short trace. figure 15. power-supply grounding connections output code input voltage (lsb) 0 fs fs - 3 / 2 lsb 1 lsb = full-scale transition 123 11... 111 11... 110 11... 101 00... 011 00... 010 00... 001 00... 000 fs 4096 figure 14a. unipolar transfer function output code input voltage (lsb) 0 +fs - 1 lsb 1 lsb = -fs 011... 111 011... 110 000... 001 000... 000 111... 111 100... 010 100... 001 100... 000 2|fs| 4096 figure 14b. bipolar transfer function
MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs 18 ______________________________________________________________________________________ ordering information (continued) pin configurations 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 n.c. ref n.c. refadj dgnd n.c. dgnd v dd ch7 ch6 ch5 ch4 sstrb din cs sclk 16 15 14 13 9 10 11 12 ch3 ch2 ch1 ch0 agnd shdn dout n.c. pdip MAX1270 max1271 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 n.c. ref refadj n.c. n.c. ch7 ch0 n.c. ch6 ch5 ch4 ch3 ch2 ch1 agnd shdn dout n.c. sstrb din n.c. n.c. cs sclk n.c. dgnd dgnd v dd ssop top view MAX1270 max1271 chip information transistor count: 4219 substrate connected to agnd part temp range pin-package inl (lsb) MAX1270aeng -40? to +85? 24 narrow pdip ?.5 MAX1270beng -40? to +85? 24 narrow pdip ? MAX1270aeai -40? to +85? 28 ssop ?.5 MAX1270beai -40? to +85? 28 ssop ? max1271 acng 0? to +70? 24 narrow pdip ?.5 max1271bcng 0? to +70? 24 narrow pdip ? max1271acai 0? to +70? 28 ssop ?.5 max1271bcai 0? to +70? 28 ssop ? max1271aeng -40? to +85? 24 narrow pdip ?.5 max1271beng -40? to +85? 24 narrow pdip ? max1271aeai -40? to +85? 28 ssop ?.5 max1271beai -40? to +85? 28 ssop ?
MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs ______________________________________________________________________________________ 19 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) pdipn.eps
MAX1270/max1271 multirange, +5v, 8-channel, serial 12-bit adcs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. pa ck ag e information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) ssop.eps package outline, ssop, 5.3 mm 1 1 21-0056 c rev. document control no. approval proprietary information title: notes: 1. d&e do not include mold flash. 2. mold flash or protrusions not to exceed .15 mm (.006"). 3. controlling dimension: millimeters. 4. meets jedec mo150. 5. leads to be coplanar within 0.10 mm. 7.90 h l 0 0.301 0.025 8 0.311 0.037 0 7.65 0.63 8 0.95 max 5.38 millimeters b c d e e a1 dim a see variations 0.0256 bsc 0.010 0.004 0.205 0.002 0.015 0.008 0.212 0.008 inches min max 0.078 0.65 bsc 0.25 0.09 5.20 0.05 0.38 0.20 0.21 min 1.73 1.99 millimeters 6.07 6.07 10.07 8.07 7.07 inches d d d d d 0.239 0.239 0.397 0.317 0.278 min 0.249 0.249 0.407 0.328 0.289 max min 6.33 6.33 10.33 8.33 7.33 14l 16l 28l 24l 20l max n a d e a1 l c h e n 1 2 b 0.068

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